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Nvidia accelerates glass substrate push, targets 2028 mass production
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According to a report by Seoul Economic Daily, Nvidia is evaluating glass substrate solutions and collaborating with German equipment maker SCHMID and other firms. Nvidia expects substrate manufacturers in South Korea and Japan to complete glass substrate development within two years, with mass production potentially starting by 2028. The article, citing SCHMID's first-half earnings call, notes that the company is working with core suppliers of Intel, Nvidia, and AMD to develop glass substrate equipment, though technical challenges in through-glass via (TGV) metallization remain and customer certification is incomplete. Nvidia has also partnered with Corning in a multi-year deal involving up to $2.7 billion investment for optical connectivity products, and with TSMC on CoPoS glass panel packaging for next-generation GPUs. The push is driven by three factors: organic substrate physical limits in advanced packaging, panel-level packaging efficiency for large AI chips like Nvidia's Rubin Ultra (estimated 7,470 sq mm), and high-speed optical interconnect needs for co-packaged optics. Industry players including Intel, Samsung, and AMD are also investing, but full mass production remains elusive, with equipment being the key bottleneck. Chinese firms BOE and Wogee Photonics are preparing glass substrate production lines, while Shengmei Shanghai has received orders for panel-level electroplating equipment.
Source report
According to Seoul Economic Daily, Nvidia is evaluating glass substrate solutions and collaborating with German equipment manufacturer SCHMID and other partners. Nvidia expects substrate makers in South Korea, Japan, and elsewhere to complete glass substrate development within two years, with commercial deployment potentially as early as 2028.
As major players enter the field, glass substrate mass production is expected to accelerate.
Nvidia Ramps Up Glass Substrate Investment
In its first-half earnings call, SCHMID stated that it is working with core suppliers of Intel, Nvidia, and AMD to jointly develop glass substrate equipment, Seoul Economic Daily reported. Currently, technical challenges remain in the metallization of Through Glass Via (TGV), and customer certification has not yet been completed.
This marks Nvidia's latest move—following its collaboration with TSMC on panel-level packaging and with Corning on optical interconnect products—to address glass substrate bottlenecks from a full supply chain perspective, accelerating the path to mass production.
Earlier, Nvidia CEO Jensen Huang met with SK Group Chairman Chey Tae-won to discuss semiconductor cooperation, including glass substrates, aiming to secure South Korea's substrate and materials supply chain.
In May of this year, Nvidia also signed a multi-year agreement with glass substrate giant Corning. Nvidia will invest up to $2.7 billion in Corning and receive warrants. Corning will build three new manufacturing plants in the U.S., expanding its domestic optical connectivity product capacity tenfold, dedicated to serving hyperscale AI data centers.
Nvidia continues to co-define CoPoS glass panel packaging with TSMC, designed to support ultra-large panel-level packaging and accommodate more HBM per package. This aims to increase bandwidth for next-generation GPUs and CPO, reduce package warpage, and improve packaging yield, with a target for mass production between 2028 and 2029.
Three Key Drivers Attracting Industry Giants
Intel began preliminary research on replacing organic substrates with glass as early as 2013, and officially released its Glass Core Substrate advanced packaging roadmap in 2023. However, Intel has yet to achieve full-scale mass production of glass substrates.
Global semiconductor giants—including Intel, Nvidia, TSMC, Samsung, and AMD—have all entered the glass substrate space, making it one of the hottest sectors in recent years. Three major application scenarios underpin this trend, with the ultimate driver being the AI computing race.
1. Advanced Packaging Substrates Hitting Physical Limits
Intel's early involvement in glass substrate R&D stemmed from its recognition that organic substrate materials used in advanced packaging are approaching their physical limits.
As Chiplet technology advances, advanced packaging is increasingly seen as a development path beyond advanced process nodes. However, with rapidly expanding package sizes and rising chip power consumption, ABF/BT organic materials face issues such as thermal expansion, warpage, and interlayer misalignment, nearing the physical limits of organic substrates.
Glass substrates serve as a material foundation for advanced packaging in the post-Moore era. Unlike organic substrates, which typically have a coefficient of thermal expansion (CTE) of 10–20 ppm/°C, glass CTE can be tuned to 3–9 ppm/°C—close to silicon's CTE of 2.5–3 ppm/°C. This reduces stress between chiplets in large-scale packaging, minimizes warpage and pattern distortion, and significantly improves packaging yield.
2. Glass Interposers in Panel-Level Packaging
Another major driver is the rapid development of panel-level packaging. AI chip die sizes are growing: Nvidia's Blackwell has a package area of approximately 2,739 mm², while the next-generation Rubin Ultra is expected to reach about 7,470 mm²—nearly nine times the area of a standard reticle.
When using 300 mm circular wafers for silicon interposers, significant edge waste occurs. In contrast, 510×515 mm rectangular glass panels achieve utilization rates exceeding 75%, substantially reducing material costs for large-scale packaging.
Thus, panel-level packaging (PLP) has emerged as another application route for glass materials: as package sizes continue to increase, the unit cost of glass interposers becomes significantly lower than that of silicon interposers or ABF organic substrates.
3. Glass Optical Platforms for High-Speed Optical Interconnects
Beyond AI computing chips, high-speed interconnects represent the third major growth driver for glass materials.
In CPO (co-packaged optics), achieving higher interconnect density, lower power consumption, and higher-frequency signal transmission requires materials with superior properties. Glass offers dielectric losses an order of magnitude lower than organic materials, with lower crosstalk and longer channel lengths, making it a preferred material choice.
At ECTC 2025 (the IEEE 75th Electronic Components and Technology Conference), researchers demonstrated TGVs with a diameter of 6 microns and an aspect ratio exceeding 15:1. Georgia Tech achieved stacked glass devices operating at 220 GHz with an insertion loss of only 0.3 dB, providing experimental evidence for future hybrid optoelectronic packaging.
Additionally, MicroLED and high-speed memory devices are expected to become new application scenarios for glass materials.
Technology Still Immature; Equipment Remains Key Bottleneck
Intel is the first company to produce engineering samples of glass substrates, but full mass production has not yet been achieved.
Industry sources indicate that Intel is not only advancing its EMIB (embedded multi-die interconnect bridge) advanced packaging technology but also expanding into MicroLED substrate advanced packaging. It is reportedly collaborating with MicroLED manufacturer AUO to develop integrated solutions for CPO and high-density computing chips.
With major industry players entering the field, accelerated technological breakthroughs are widely expected.
At BOE's annual IPC 2026 event on September 22, BOE Chairman Chen Yanshun stated that the company is preparing to invest in a mass production line for semiconductor glass substrate carriers.
Woged Photonics recently disclosed that glass substrates, leveraging their excellent optical transparency and extremely low high-frequency dielectric loss—combined with core TGV processes—significantly shorten signal paths and reduce per-bit power consumption. Some industry players are actively promoting the application of glass substrates in computing network hardware infrastructure. The company has深耕多年 in the TGV glass substrate circuit board sector and is actively advancing product development and sample validation in related fields.
Regarding electroplating equipment—one of the key bottlenecks in panel-level packaging—Shengmei Shanghai recently disclosed that it took the lead in 2022 in developing horizontal electroplating technology. The company now supports panel sizes including 310×310 mm, 510×515 mm, and 600×600 mm. This year, it received its first order for a 510×515 mm panel-level horizontal electroplating mass production tool from an existing domestic advanced packaging customer, with delivery scheduled for Q1 2027. Additionally, the company received an order for a 310×310 mm panel-level horizontal electroplating evaluation tool from a leading panel packaging customer in Asia, to be delivered within this year.
(Source: Shanghai Securities News)
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Nvidia pushes glass substrate development, targets 2028 mass production for AI chips