Chip startup TYLsemi emerges from stealth with $43M to simplify custom chiplet-based processor design

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TYLsemi Emerges from Stealth with $43M to Simplify Custom AI Chip Development

A new semiconductor firm, TYLsemi (pronounced "Tile Semi"), has publicly launched this month, announcing $43 million in early-stage funding. The company aims to simplify the development of custom processors for AI infrastructure.

While dozens of contract chip designers can develop custom processors of varying complexity, only a few offer custom silicon design services using standard chiplets to accelerate and de-risk the development cycle. TYLsemi intends to join this select group. Tom's Hardware spoke with the founders to understand how the nascent business plans to succeed.

Emerging from Stealth

Rather than competing solely as another custom ASIC design house, TYLsemi plans to offer reusable, standards-based connectivity, power delivery, and—eventually—memory chiplets. Customers can combine these with their own differentiating compute silicon to build a unique system-in-package (SiP).

For companies that do not wish to conduct semiconductor development themselves, TYLsemi will provide an end-to-end service. This includes the design and implementation of a differentiating chiplet, packaging, qualification, and high-volume production. This model essentially enables companies with no silicon development expertise to offer their own multi-chiplet processors.

TYLsemi was co-founded by Mohit Gupta and Sunil Bhardwaj, semiconductor veterans with experience at Alphawave, SiFive, Cadence, and Rambus. Both have led global engineering, operations, and business teams and possess extensive experience with standard and custom silicon.

Mohit Gupta, co-founder and CEO of TYLsemi, believes the time is right for a company specializing in pre-approved chiplets and custom ASIC design.

"Chiplets have been discussed for seven or eight years, but several things have changed in the last three or four years," Gupta told Tom's Hardware Premium.

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"First, advanced packaging has matured significantly. There are now multiple 2.5D and 3D integration options in volume production. Customers are not limited to one packaging technology or supplier; there are options from foundries and OSATs, including TSMC, Intel, ASE, and Amkor.

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"Second, die-to-die standards have arrived. In the past, most chiplet implementations relied on proprietary interfaces. UCIe is now moving into production deployments, including at hyperscalers, which makes heterogeneous integration much more practical.

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"Third, supply-chain resilience has become critical. Customers increasingly want modular and potentially multi-source strategies rather than a single point of failure. Those factors have created an environment that did not exist four or five years ago."

Focus on AI Accelerators

AI accelerators will be among the primary applications to benefit from multi-chiplet design, as seen with AMD and Nvidia.

"The AI accelerator market is on track to reach $604 billion by 2033, and custom silicon XPUs built for specific hyperscaler workloads are the fastest-growing segment," Gupta said.

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"At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio. TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-die connectivity, XPU-aware design, packaging, and integration — giving customers a fast, proven path to AI-era silicon."

The Economics of Chiplets

The vast majority of AI and HPC accelerators today feature large die sizes, often approaching the size of a reticle. However, as modern process technologies become more complex, foundries have increased their pricing for new nodes. A leading-edge wafer used to cost around $15,000 to process five years ago; today, that price is around $30,000.

As a result, large chips near the reticle limit on a leading-edge node are only an option for a select few designers who can afford it. For newcomers, multi-chiplet designs enabled by advanced packaging and standardized interconnects like UCIe are becoming far more practical.

"Once dies get into the 500 – 600 mm² range, the yield curve becomes increasingly difficult. Timing closure on a reticle-sized die is also challenging," Gupta explained. "I have worked on a reticle-sized accelerator, and getting from 99% to the final 1% can require disproportionately more engineering effort."

TYLsemi estimates that its chiplet approach could reduce total cost of ownership by 57% at a volume of 100,000 devices. The comparison is as follows:

• Monolithic Design: $350 million for a single 700 mm² 3nm-class chip (estimated unit price: $3,000).
• Chiplet (SiP) Design: $150 million for a design combining a 500 mm² 3nm-class compute die with four 100 mm² I/O chiplets built on an N-1 process (estimated unit price: $600).