AMD unveils MI455X AI accelerator, Helios rack-scale architecture to rival Nvidia

At AMD's Advancing AI event this week, the company disclosed further details of its upcoming MI455X GPU and the Helios rack-scale architecture, which will integrate 72 GPUs into a single coherent accelerator. This represents AMD's largest such system to date and its first to directly compete with Nvidia's NVL72 rack-scale design, used in the Blackwell and Rubin generations.

AMD described the MI455X as "by leaps and bounds the most advanced AI accelerator we’ve ever built." Based on available information, it is the most competitive product AMD has produced—both at the chip level and at rack scale—against Nvidia's dominant position in the AI compute race.

Chip Architecture and Packaging

The full MI455X GPU is a massive chip containing 320 billion transistors, built using advanced packaging technologies:

• Four Accelerator Complex Dies (XCDs) are stacked on top of each Fabric and Cache Die (FCD) using hybrid bonding.
• The two FCDs are each joined to:
• Six stacks of HBM4
• Two I/O dies
• One another, using TSMC's CoWoS-L technology

This chiplet design allows AMD to use the most advanced TSMC 2N gate-all-around (GAA) process on the XCDs, where it is most beneficial for power and performance. The FCDs and I/O dies, which contain elements that do not benefit from the densest process technologies, are fabricated on TSMC N3P.

CDNA 5 Architecture Changes

CDNA 5 represents a significant shift in the CDNA architecture. AMD now calls the fundamental building block of the CDNA 5 Accelerator Complex Die a "Work Group Processor" (WGP) instead of a "Compute Unit," though the basic layout of the rest of the XCD remains largely similar.

• The number of WGPs on the MI455X remains 256, unchanged from the MI355X.
• Since the number of fundamental compute resources has not changed, per-WGP throughput on the CDNA 5 MI455X must be significantly higher to deliver its large performance boost.

Wavefront Size Change

CDNA 5 marks a major shift in the programming model for an Instinct GPU:

• The width of a wavefront (a group of work items or threads addressed by each WGP) is now 32 instead of 64.
• AMD states this improves instruction latency, branch divergence penalties, and register pressure.
• A 32-wide approach increases architectural flexibility for interacting with different tensor tile sizes and mapping compute kernels to hardware.
• RDNA GPUs have used a native wavefront size of 32 since their introduction.

Compute Performance Enhancements

CDNA 5 greatly enhances compute performance over CDNA 4, theoretically doubling and in some cases quadrupling the peak FLOPS possible from the chip. The MI455X particularly benefits lower-precision floating-point formats now common in inference:

• OCP MXFP8 and MXFP4 formats are theoretically up to 4X faster than on the CDNA 4 MI355X.

Theoretical Peak FLOPS Comparison

| Format | Instinct MI355X | Instinct MI455X | Nvidia Rubin | |--------|----------------|----------------|--------------| | NVFP4 (dense) | -- | -- | 35 PF | | OCP MXFP4 | 10 PF | 40.26 PF | -- | | OCP MXFP6 | 10 PF | 20.13 PF | 17.5 PF | | OCP MXFP8 | 10 PF | 20.13 PF | 17.5 PF | | Matrix FP16/BF16 | 2.5 PF | 5.03 PF | 4 PF | | Vector FP16 | 157.3 TF | 315 TF | -- | | Matrix FP32 | 157.3 TF | 315 TF | 400 TF | | Vector FP32 | 157.3 TF | 315 TF | 130 TF |

On paper, the MI455X offers peak performance that exceeds what Nvidia has shown for Rubin so far. Combined with the Helios rack-scale architecture—which gives AMD the same 72-GPU coherent domain as Nvidia's NVL72—AMD is more competitive in the AI data center capacity race than ever before. This is translating into real customer wins, with AMD announcing pivotal deals with Microsoft and Anthropic this week.

Caveats on Real-World Performance

AMD itself cautioned against drawing too many conclusions from these head-to-head peak FLOPS numbers. The realized performance of these GPUs in real-world applications is likely to be much lower in practice. The ongoing challenge will be to optimize software and applications to achieve as much of that theoretical performance as possible.

Additional Improvements

Beyond general compute improvements, AMD is also touting improved transcendental math performance from the CDNA 5 Transcendental Unit, which has wide-reaching implications for performance on essential AI functions such as:

• Softmax
• Neural network activations
• Attention mechanisms

AMD states that the CDNA 5 Transcendental Unit doubles throughput compared to the previous generation.