TYLsemi emerges from stealth with $43M to simplify custom chiplet-based AI processor design

A new semiconductor firm, TYLsemi (pronounced "Tile Semi"), publicly revealed itself this month alongside $43 million in early-stage funding and an ambitious plan to simplify the development of custom processors for AI infrastructure.

Dozens of contract chip designers can develop custom processors of varying complexity. However, only a few companies can offer custom silicon design services using standard chiplets to accelerate and de-risk the development cycle. TYLsemi aims to join their ranks. We spoke to their founders to find out how the nascent business might pull it off.

Emerging from Stealth

Rather than compete solely as another custom ASIC design house, TYLsemi intends to offer reusable, standards-based connectivity, power delivery, and eventually memory chiplets that customers can combine with their own differentiating compute silicon to build a unique system-in-package.

For companies that do not intend to conduct semiconductor development themselves, TYLsemi will also provide an end-to-end service that includes:

• Design and implementation of a differentiating chiplet
• Packaging
• Qualification
• High-volume production

This essentially enables companies without any silicon development skills to offer their own multi-chiplet processors.

Industry Veterans at the Helm

TYLsemi was co-founded by Mohit Gupta and Sunil Bhardwaj, semiconductor veterans who have led global engineering, operations, and business teams at Alphawave, SiFive, Cadence, Rambus, and other chip companies. Together, they have extensive experience with both standard and custom silicon.

Mohit Gupta, co-founder and chief executive of TYLsemi, believes the time is right to establish a company specializing in pre-approved chiplets and custom ASIC design.

"Chiplets have been discussed for seven or eight years, but several things have changed in the last three or four years," Gupta told Tom's Hardware Premium.

Key changes driving the chiplet market:

• Advanced packaging has matured significantly. There are now multiple 2.5D and 3D integration options in volume production. Customers are not limited to one packaging technology or supplier; options exist from foundries and OSATs, including TSMC, Intel, ASE, and Amkor.

• Die-to-die standards have arrived. In the past, most chiplet implementations relied on proprietary interfaces. UCIe is now moving into production deployments, including at hyperscalers, making heterogeneous integration much more practical.

• Supply-chain resilience has become critical. Customers increasingly want modular and potentially multi-source strategies rather than a single point of failure.

"Those factors have created an environment that did not exist four or five years ago," Gupta said.

Focus on AI Accelerators

AI accelerators will be among the primary applications to benefit from multi-chiplet design, as we have already learned from AMD and Nvidia.

"The AI accelerator market is on track to reach $604 billion by 2033, and custom silicon XPUs built for specific hyperscaler workloads are the fastest-growing segment," Gupta said. "At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio. TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-die connectivity, XPU-aware design, packaging, and integration — giving customers a fast, proven path to AI-era silicon."

The Economics of Chiplets

The vast majority of AI and HPC accelerators today feature large die sizes, in many cases approaching the size of a reticle. However, as modern process technologies become more complex, foundries tend to increase their quotes for new nodes.

• A leading-edge wafer used to cost around $15,000 to process approximately five years ago.
• Today, that price is around $30,000.

As a result, large chips near the reticle limit on leading-edge nodes become an option only for a select few chip designers who can afford it. For newcomers, multi-chiplet designs enabled by advanced packaging and standardized interconnects such as UCIe start to make much more sense.

"Once dies get into the 500–600 mm² range, the yield curve becomes increasingly difficult. Timing closure on a reticle-sized die is also challenging," Gupta explained. "I have worked on a reticle-sized accelerator, and getting from 99% to the final 1% can require disproportionately more engineering effort."

Cost Comparison: Monolithic vs. Chiplet Approach

TYLsemi estimates that its chiplet approach could reduce total cost of ownership by 57% at a volume of 100,000 devices:

| Metric | Monolithic Chip | Chiplet SiP | |--------|----------------|-------------| | Design | 700 mm² 3nm-class | 500 mm² 3nm-class compute die + four 100 mm² I/O chiplets on N-1 process | | Total Cost | $350 million | $150 million | | Unit Price | $3,000 | ~$600 |