SK hynix and Samsung unveil competing thermal architectures for next-gen AI memory HBM5
On May 26, 2026, SK hynix announced 'iHBM,' a thermal packaging architecture integrating cooling elements into the HBM interface layer, reducing thermal resistance by over 30% for HBM5 AI accelerators. Shortly after, at Computex 2026 in Taipei, Samsung displayed its HBM5 mockup with a 'Heat Path Block' cooling structure. Both innovations target heat dissipation challenges in dense AI data centers, intensifying competition between the two memory giants in the AI memory market.
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Samsung shows first HBM5 mockup with Heat Path Block cooling at Computex 2026
At Computex 2026 in Taipei, Samsung displayed its first physical mockup of HBM5 memory, the eighth-generation AI memory, paired with a new in-package cooling structure called Heat Path Block (HPB). The HPB technology builds separate thermal pillars to address heat bottlenecks in the die-to-die interface connecting memory to the processor. This follows rival SK hynix's unveiling of its own iHBM thermal design last week, indicating an intensifying thermal management race. Samsung also confirmed it will fabricate HBM5's base die on its in-house 2nm process, down from the 4nm node used for HBM4 and HBM4E. The article includes links to related roadmaps for HBM, Nvidia enterprise GPUs, AI accelerators, desktop GPUs, and 3D NAND.
Latest from Tom's HardwareSamsung shows first HBM5 mockup with Heat Path Block cooling — thermal race with SK hynix shaping up
At Computex 2026 in Taipei, Samsung displayed its first physical mockup of HBM5 memory, the eighth-generation AI memory, featuring a new in-package cooling structure called Heat Path Block (HPB). This technology uses thermal pillars to pull heat from inside the stack to a spreader, addressing the heat bottleneck in the die-to-die interface. The announcement follows rival SK hynix's recent unveiling of its own iHBM thermal architecture, intensifying the competition in thermal management for next-gen AI memory. Samsung also confirmed it will fabricate HBM5's base die on its in-house 2nm process, down from the 4nm node used for HBM4 and HBM4E.
Latest from Tom's HardwareSamsung shows first HBM5 mockup with Heat Path Block cooling at Computex 2026
At Computex 2026 in Taipei, Samsung displayed its first physical mockup of HBM5 memory, the eighth-generation AI memory, paired with a new in-package cooling structure called Heat Path Block (HPB). The HPB technology builds separate thermal pillars to address heat bottlenecks in the die-to-die interface connecting memory to the processor. This follows rival SK hynix's unveiling of its own iHBM thermal design last week, indicating an intensifying thermal management race. Samsung also confirmed it will fabricate HBM5's base die on its in-house 2nm process, a node shrink from the 4nm node used for HBM4 and HBM4E. The article includes links to related roadmaps for HBM, Nvidia enterprise GPUs, AI accelerators, desktop GPUs, and 3D NAND.
Latest from Tom's HardwareSK hynix unveils 'iHBM' thermal architecture that cools AI memory at the source — integrated cooling elements inside HBM interface cut thermal resistance by 30%, target next-gen HBM5 accelerators and dense AI data centers
SK hynix has announced a new thermal management architecture called 'iHBM' designed to cool AI memory at the source. The innovation integrates cooling elements directly inside the High Bandwidth Memory (HBM) interface, reducing thermal resistance by 30%. This technology is aimed at next-generation HBM5 accelerators and high-density AI data centers, where heat dissipation is a critical challenge. By addressing thermal bottlenecks at the memory level, iHBM could improve performance and reliability in AI workloads. The announcement highlights SK hynix's focus on advanced packaging and thermal solutions to support the growing demands of AI computing.
"site:tomshardware.com" - Google NewsSK hynix unveils 'iHBM' thermal architecture that cools AI memory at the source — integrated cooling elements inside HBM interface cut thermal resistance by 30%, target next-gen HBM5 accelerators and dense AI data centers
SK hynix has announced iHBM, a new thermal packaging architecture for high-bandwidth memory (HBM) used in AI accelerators. The technology integrates cooling elements directly into the HBM interface layer, reducing thermal resistance by over 30%. This innovation aims to prevent performance-killing thermal throttling in next-generation HBM5-based AI accelerators and dense AI data centers. By cooling memory at the source, iHBM ensures stable operating characteristics even under high-temperature and high-load conditions, addressing a critical bottleneck in AI system performance.
Latest from Tom's HardwareSK hynix unveils 'iHBM' thermal architecture that cools AI memory at the source
SK hynix announced 'iHBM,' a new thermal packaging architecture for High Bandwidth Memory (HBM) used in AI accelerators. The technology integrates cooling elements directly into the HBM interface layer, reducing thermal resistance by over 30%. This innovation aims to prevent performance-degrading thermal throttling in next-generation HBM5 accelerators and dense AI data centers. The announcement was made via an official press release on May 26, 2026, and reported by Tom's Hardware. The solution is designed to address the growing heat dissipation challenges in high-performance AI computing environments.
Latest from Tom's HardwareSK hynix unveils 'iHBM' thermal architecture that cools AI memory at the source
SK hynix has announced iHBM, a new thermal packaging architecture that embeds integrated cooling elements (ICEs) directly into the HBM interface layer. This innovation reduces thermal resistance by over 30%, enabling stable operation in high-temperature environments and preventing performance-killing thermal throttling in AI accelerators. The technology is specifically designed for next-generation HBM5 accelerators and dense AI data centers, addressing critical heat management challenges as AI workloads intensify. The announcement was made on May 26, 2026, and represents a significant advancement in memory heat management for high-performance computing.
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